This invention relates to a random access memory and more particularly to a bidirectional data byte aligner apparatus for transferring one or more bytes of a digital word to and from one or more memory locations within one memory cycle time period.
A computer or data processing system usually comprises a memory subsystem having a plurality of memory locations for the storage of digital words made up of a specific number of bits such as 8, 16, 24 or 32. The computer architecture for some prominent 32 bit general register machines employs variable length instructions represented by a sequence of bytes with the first one or two bytes specifying the operation to be performed and subsequent bytes specifying the operands. The average instruction is approximately three bytes in length, although in one computer the instructions may be from one to fifty-six bytes long. Storage of a mixture of variable length instructions and data in a 32 bit longword memory achieves maximum utilization of the memory storage space available if, for example, part of a 32 bit instruction or data word is stored in the same memory address as a 16 bit instruction or data word and the remainder in a subsequent memory address.
In the prior art, efficient utilization of memory space has been accomplished by a combination of hardware and software techniques. Often, more than one memory cycle time period is required when part of an instruction or data word is stored at one memory address and the other part is stored at a subsequent memory address location. In other cases, only certain addresses of a memory system are available for storage of multiple byte words, or provision is made for converting an unaligned memory request into a sequence of shorter aligned requests, which requires several memory cycle time periods. The result has been that efficient utilization of memory space is accomplished, but the processing speed of the computer is reduced.
The prior art has placed restrictions upon byte addressability in a memory system resulting in improved memory utilization but decreased speed of operation. It is desirable to be able to access any sequence of one, two or four bytes beginning at any byte address in a memory system without any alignment constraints placed on the programmer or on the operating system in order to achieve maximum system performance with minimum hardware.